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Stanford-Led Skyscraper-Style Chip Design Boosts Electronic Performance By Factor of a Thousand

By Stanford Report

December 14, 2015

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Stanford University engineers are leading a multi-institution effort to develop a revolutionary high-rise architecture for computing. The processors and memory chips in modern computer systems are laid out like single-story structures in a suburb, but this suburban-style layout wastes time and energy.

The research team is pursuing a more city-like design, which involves building layers of processors and memory directly atop one another, connected by millions of electronic elevators that can move more data over shorter distances than traditional wires while also using less energy. The key will be using non-silicon materials that can be fabricated at much lower temperatures than silicon, so processors can be built on top of memory without the new layer damaging the layer below.

The team describes the approach as Nano-Engineered Computing Systems Technology (N3XT), and has demonstrated a working prototype of a high-rise chip. N3XT high-rise chips are based on carbon nanotube transistors (CNTs), which are faster and more energy efficient than silicon processors. Moreover, in the N3XT architecture, the CNTs can be manufactured and placed over and below other layers of memory. N3XT systems will "outperform conventional approaches by a factor of a thousand," says Stanford professor H.-S. Philip Wong.

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