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3-D Chip Design Challenges

By PhysOrg.com

February 23, 2010

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Engineers from the European research agency IMEC discussed the design challenges of stacking layers of silicon dies using vertical copper interconnects, or through-silicon vias (TSVs), at the recent International Solid-State Circuit Conference. Chipmakers are optimistic that TSVs will enable them to meet the design challenges of three-dimensional (3D) chip technology. TSVs would allow larger bandwidth between memory and logic, as they can be placed 200 micrometers apart, which would significantly cut down on bottlenecking.

Heat will be an issue with stacked chips because it spreads unevenly due to poorly conductive adhesives that hold the thin wafers together, and can lead to chip unreliability and data corruption. Copper TSVs contract faster when cooling than their silicon counterparts, and the mechanical stress can have a negative impact on transistor performance.

Chip designers also will need to create blank areas or gaps on the chip to account for TSV placement to transistors, which can change parameters such as threshold voltage and drive current.

From PhysOrg.com
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